Minimized power consumption for scan-based BIST
نویسندگان
چکیده
1 This work was supported by DFG grant WU 245/1-3 Abstract Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture are analyzed, the modules and modes with the highest power consumption are identified, and design modifications to reduce power consumption are proposed. The design modifications include some gating logic for masking the scan path activity during shifting, and the synthesis of additional logic for suppressing random patterns which do not contribute to increase the fault coverage. These design changes reduce power consumption during BIST by several orders of magnitude, at very low cost in terms of area and performance.
منابع مشابه
Strategies and Techniques for Optimizing Power in BIST: A Review
Power dissipation is a challenging problem in current VLSI designs. In general the power consumption of device is more in the testing mode than in the normal system operation. Built in self test (BIST) and scan-based BIST are the techniques used for testing and detecting the faulty components in the VLSI circuit. Linear Feedback Shift Register (LFSR) in BIST generates pseudo-random patterns for...
متن کاملSegment Weighted Random Bist (swr-bist) Technique for Low Power Testing
This paper presents a segment weighted random built-in self test (SWR-BIST) technique for low power testing. This technique divides the scan chain into segments of different weights. Heavily weighted segments have more biased probability than lightly weighted segments. Heavily weighted segments are placed closer to the end of scan chain than the lightly weighted segments so the scan-in transiti...
متن کاملMultiple Scan Chain Design Technique for Power Reduction during Test Application in BIST
Multiple scan chain has been used in DFT (design for test) architectures primarily to reduce test application time. Since power is an emerging problem, in this paper, we present a design technique for multiple scan chain in BIST (Built-In Self Test) to reduce average power dissipation and test application time, while maintaining the fault coverage. First, we partition the scan chain into a set ...
متن کاملAn Efficient Online BIST Architecture for NoCs
This paper presents an offline/online concurrent scan based built-in-self-test (scan-BIST) method for a Network-onChip (NoC) based SoC. The proposed architecture contains a special scan cell and an Embedded Test Core (ETC) as its test source. The ETC performs a static flow control and a centric average power consumption control during the proposed test mechanism. To reduce the test vector traff...
متن کاملA Gated Clock Scheme for Low Power Scan-Based BIST
In this paper, we present a new low power scan-based BIST technique which can reduce the switching activity during test operation. The proposed low power /energy technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path.
متن کامل